This invention relates generally to pulse code modulation transmission systems and more specifically to a logic network which is adapted to be disposed in a signal transmission line for reshaping and retiming the data stream to obviate amplitude and phase distortion introduced by the transmission line.
Transmission of digital data over transmission lines results in degradation of the signal waveform, as a function of the characteristics and length of the transmission line. The degradation has two basic components, attenuation and phase distortion. Phase distortion may be defined as the time displacement between the actual signal level transition and the nominal transition, divided by the nominal data bit interval. Where cable lengths between a data transmitter and a receiver are short relative to the transmission rate employed, it may be sufficient to operate without compensation in the lines. However, where the cable lengths are long such that distortion becomes excessive, for proper reception, it is necessary to provide a repeater which will regenerate pulse durations or the transition time instants.
The present invention is concerned with the design of such a regenerative repeater network which may be used to regenerate non-return to zero (NRZ) data streams which is a common mode of encoding digital data for asynchronous (unclocked) transmission. Many known regenerative repeater networks will not operate when NRZ encoding is employed. This is due to the fact that NRZ encoded data does not include a spectral component at its fundamental clock frequency. The present invention includes a novel transition detector which operates to generate this fundamental clock frequency component.
In accordance with the teachings of this invention, the incoming data stream is applied to the "Data" terminal of a so-called "D-type" flip-flop, which, as is well known in the art, is a bistable circuit which produces at its output the signal levels existing at its "Data" terminal at the instant that a predetermined clock signal transition is applied to its "Clock" input terminal. The input data stream to be regenerated is also applied to a novel transition detector network designed to produce short reference pulses each time the incoming data stream undergoes either a positive or a negative transition from an arbitrary reference point. These reference pulses will hereinafter be referred to as "T" pulses, for convenience.
The T pulses are applied as a first input to a "phase-lock loop" network. The phase-lock loop includes a free-running voltage controlled oscillator (VCO) clock, an amplifier and a phase comparator network. More specifically, the T pulses are applied to one input of the phase comparator and the output from the VCO clock is connected to a second input. At phase lock, a clock transition divides a T pulse equally so that the phase comparator does not produce an error output signal. However, if the VCO deviates in phase, a voltage signal is developed at the output of the phase comparator which causes the VCO to alter its frequency in a direction to reduce the error signal to zero. The output from the VCO clock is applied to the "Clock" terminal of the D-type flip-flop and is used to trigger the flip-flop and thereby gate the data stream to the output cable.
In implementing the regerative repeater, conventional commercially available ECL integrated circuits are utilized throughout. As such, packaging of the repeater is facilitated.